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1 for more information www.linear.com/LTM4649 typical a pplica t ion fea t ures descrip t ion 10a step-down dc/dc module regulator the lt m ? 4649 is a complete 10a high efficiency switching mode step-down dc/dc module ? regulator in a 9mm 15mm 4.92 bga package. included in the package are the switching controller, power fets, inductor, and all sup - port components. operating over an input voltage range of 4.5v to 16v, the l tm4649 supports an output voltage range of 0.6v to 3.3v, set by a single external resistor. this high efficiency design delivers 10a continuous current. only bulk input and output capacitors are needed. high switching frequency and a current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. the device supports frequency synchronization, programmable multiphase operation, spread spectrum, output voltage tracking for supply rail sequencing. fault protection features include overvoltage protection, overcurrent protection. the LTM4649 is offered in a small thermally enhanced 9mm 15mm 4.92mm bga pack - age. the LTM4649 is available with snpb (bga) or rohs compliant terminal finish. efficiency and power loss at 12v and 5v input current derating: 12v input, 1.5v out , no heat sink 4.5v to 16v input, 1.5v output dc/dc module regulator a pplica t ions n 10a dc output current n input voltage range: 4.5v to 16v n output voltage range: 0.6v up to 3.3v n no heat sink or current derating up to 85c ambient temperature n 1.5% total dc voltage output error n multiphase operation with current sharing n remote sense amplifier n built-in general use temperature monitor n selectable pulse-skipping mode/burst mode ? operation for high efficiency at light load n soft-start/voltage t racking n protection: output overvoltage and over current foldback n 9mm 15mm 4.92mm bga package n telecom, networking and industrial equipment n point of load regulation l , lt, ltc, ltm, burst mode, module, polyphase, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. other patents pending. v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd 0.1f 100f 6.3v 2 6.65k 22f 16v 2 v in 4.5v to 16v v out 1.5v 10a clkout 4649 ta01a load current (a) 0 65 efficiency (%) power loss (w) 70 75 80 85 90 95 0 0.5 1.0 1.5 2.0 2.5 3.0 2 4 6 8 4649 ta01b 10 v in = 12v v in = 5v ambient temperature (c) 0 0 load current (a) 2 4 6 8 12 20 40 60 80 4649 ta01c 100 120 10 400lfm 200lfm 0lfm 4649fa LTM4649
2 for more information www.linear.com/LTM4649 a bsolu t e maxi m u m r a t ings v in ............................................................. C0 .3v to 18v v out .......................................................... C0 .3v to 3.6v intv cc , pgood, run (note 5) .................... C0 .3v to 6v mode, clkin, track/ss, diffp, diffn, diffout, phasmd ............................... C 0.3v to intv cc v fb ............................................................ C0 .3v to 2.7v comp (note 6) .......................................... C 0.3v to 2.7v intv cc peak output current (note 6) .................. 100 ma internal operating temperature range (note 2) .................................................. C 55c to 125c storage temperature range .................. C 55c to 125c peak solder reflow body temperature ................. 245 c (note 1) p in c on f igura t ion pgood mode temp phmode clkin a 1 2 3 4 5 6 7 8 9 10 11 b c d bga package 68-lead (9mm 15mm 4.92mm) e f g v out_lcl diffout track/ss top view diffn diffp clkout gnd gnd v out gnd freq v in nc nc sw fb comp intv cc run t jmax = 125c, ja = 14c/w, jcbottom = 5c/w, jctop = 20c/w weight = 1.0g o r d er i n f or m a t ion part number pad or ball finish part marking* package type msl rating tempera ture range (note 2) device finish code LTM4649ey#pbf sac305 (rohs) LTM4649y e1 bga 3 C40c to 125c LTM4649iy#pbf sac305 (rohs) LTM4649y e1 bga 3 C40c to 125c LTM4649iy snpb (63/37) LTM4649y e0 bga 3 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? pb-free and non-pb-free part markings: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and t ray drawings: www .linear.com/packaging 4649fa LTM4649
3 for more information www.linear.com/LTM4649 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v per typical application. symbol parameter conditions min typ max units v in input dc voltage l 4.5 16 v v out(range) output voltage range l 0.6 3.3 v v out(dc) output voltage, total variation with line and load c in = 10f 1,c out = 100f ceramic, 100f poscap, r fb = 6.65k, mode = gnd, v in = 4.5v to 16v, i out = 0a to 10a l 1.477 1.50 1.523 v input specifications v run run pin on threshold v run rising 1.1 1.25 1.4 v v run(hys) run pin on hysteresis 150 mv i q(vin) input supply bias current v in = 12v, v out = 1.5v, burst mode operation v in = 12v, v out = 1.5v, pulse-skipping mode v in = 12v, v out = 1.5v, switching continuous shutdown, run = 0, v in = 12v 5 15 75 70 ma ma ma a i s(vin) input supply current v in = 12v, v out = 1.5v, i out = 10a 1.5 a output specifications i out(dc) output continuous current range v in = 12v, v out = 1.5v (note 4) 0 10 a v out(line) v out line regulation accuracy v out = 1.5v, v in from 4.5v to 16v i out = 0a l 0.010 0.04 %/v v out(load) v out load regulation accuracy v out = 1.5v, i out = 0a to 10a, v in = 12v (note 4) l 0.15 0.5 % v out(ac) output ripple voltage i out = 0a, c out = 100f ceramic, 100f poscap, v in = 12v, v out = 1.5v 15 mv v out(start) turn-on overshoot c out = 100f ceramic, 100f poscap, v out = 1.5v, i out = 0a, v in = 12v 20 mv t start turn-on time c out = 100f ceramic, 100f poscap, no load, track/ss = 0.01f, v in = 12v 5 ms v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 100uf ceramic, 100f poscap, v in = 12v, v out = 1.5v 60 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, c out = 100f ceramic, 100f poscap, v in = 12v, v out =1.5v 20 s i outpk output current limit v in = 12v, v out = 1.5v (note 4) 12 a control specifications v fb voltage at v fb pin i out = 0a, v out = 1.5v l 0.593 0.60 0.607 v i fb current at v fb pin (note 6) C12 C25 na v ovl feedback overvoltage lockout l 0.64 0.66 0.68 v i track/ss track pin soft-start pull-up current track/ss = 0v 1.0 1.2 1.4 a t on(min) minimum on-time (note 3) 90 ns r fbhi resistor between v out_lcl and v fb pins 9.90 10 10.10 k diffp, diffn cm range common mode input range v in = 12v, run > 1.4v 0 3.6 v v diffout(max) maximum diffout voltage i diffout = 300a intv cc -1.4 v v os input offset voltage v osns + = v diffout = 1.5v, i diffout = 100a 4 mv a v differential gain 1 v/v sr slew rate 2 v/s 4649fa LTM4649
4 for more information www.linear.com/LTM4649 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v per typical application. symbol parameter conditions min typ max units gbp gain bandwidth product 3 mhz cmrr common mode rejection (note 6) 60 db i diffout diffout current sourcing 2 ma r in input resistance diffp, diffn to gnd 80 k v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C10 10 % % v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v intv cc linear regulator v intvcc internal v cc voltage 4.8 5 5.2 v v intvcc load reg intv cc load regulation i cc = 0ma to 50ma 0.9 % oscillator and phase-locked loop f sync sync capture range 250 800 khz f s nominal switching frequency 400 450 500 khz r mode mode input resistance 250 k v ih_clkin clock input level high 2.0 v v il_clkin clock input level low 0.8 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. notes are automatically numbered when you apply the note style. note 2: the LTM4649 is tested under pulsed load conditions such that t j t a . the LTM4649e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4649i is guaranteed to meet specifications over the C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the minimum on-time condition is tested at wafer sort. note 4: see output current derating curves for different v in , v out and t a . note 5: guaranteed by design. note 6: 100% tested at wafer level. 4649fa LTM4649
5 for more information www.linear.com/LTM4649 typical p er f or m ance c harac t eris t ics 5v in , 1v out load transient 5v in , 1.5v out load transient 12v in , 1v out load transient 12v in , 1.5v out load transient 5v in , 2.5v out load transient 12v in , 2.5v out load transient 12v in efficiency 5v in efficiency ccm, burst mode and pulse- skipping mode efficiency load current (a) 0 90 95 100 8 4649 g01 85 80 2 4 6 10 75 70 65 efficiency (%) v out = 1v, 450khz v out = 1.2v, 450khz v out = 1.5v, 450khz v out = 2.5v, 750khz v out = 3.3v, 750khz load current (a) 0 90 95 100 8 4649 g02 85 80 2 4 6 10 75 70 65 efficiency (%) v out = 1v, 450khz v out = 1.2v, 450khz v out = 1.5v, 450khz v out = 2.5v, 450khz v out = 3.3v, 450khz load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 4649 g03 30 20 10 0 90 100 ccm pulse- skippping burst mode operation v in = 12v v out = 1.5v v out 100mv/div ac i out 5a/div ac 50s/div 5v in , 1v out , 5a to 10a load step c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g04 v out 100mv/div ac i out 5a/div ac 50s/div 12v in , 1v out , 5a to 10a load step c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g05 v out 100mv/div ac i out 5a/div ac 50s/div 5v in , 1.5v out , 5a to 10a load step c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g06 v out 100mv/div ac i out 5a/div ac 50s/div 5v in , 2.5v out , 5a to 10a load step c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g08 v out 100mv/div ac i out 5a/div ac 50s/div 12v in , 2.5v out , 5a to 10a load step, 750khz c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g09 v out 100mv/div ac i out 5a/div ac 50s/div 12v in , 1.5v out , 5a to 10a load step c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g07 4649fa LTM4649
6 for more information www.linear.com/LTM4649 typical p er f or m ance c harac t eris t ics soft-start with full load short-circuit protection with no load short-circuit protection with full load 5v in , 3.3v out load transient 12v in , 3.3v out load transient soft-start with no load v out 100mv/div ac i out 5a/div ac 50s/div 5v in , 3.3v out , 5a to 10a load step c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g10 v out 100mv/div ac i out 5a/div ac 50s/div 12v in , 3.3v out , 5a to 10a load step, 750khz c out = 2 ? 220f 4v ceramic capacitor no c ff capacitor 4649 g11 v out 0.5v/div v sw 10v/div i in 1a/div 20ms/div 12v in , 1.5v out i o = 0a start-up c ss = 0.1f 4649 g12 v out 0.5v/div v sw 10v/div i in 1a/div 20ms/div 12v in , 1.5v out i o = 10a start-up c ss = 0.1f 4649 g13 v out 0.5v/div v sw 10v/div i in 1a/div 20s/div 12v in , 1.5v out short circuit with no load c out = 2 ? 220f 4v ceramic capacitor 4649 g14 v out 1v/div v sw 10v/div i in 1a/div 20s/div 12v in , 1.5v out short circuit with full load c out = 2 ? 220f 4v ceramic capacitor 4649 g15 4649fa LTM4649
7 for more information www.linear.com/LTM4649 p in func t ions gnd (a1-a5, a7-a11, b1, b9-b11, e1, f3, f5, g1-g7): ground pins for both input and output returns. all ground pins need to connect with large copper areas underneath the unit. temp (a6): onboard temperature diode for monitoring the vbe junction voltage change with temperature. see the applications information section. clkin (b3): external synchronization input to phase de - tector pin. a clock on this pin will enable synchronization with for ced continuous operation. see the applications information section. phmode (b4): this pin can be tied to gnd, tied to intv cc or left floating. this pin determines the relative phases between the internal controllers and the phasing of the clkout signal. see table 2 in the operation section. mode (b5): mode select input. connect this pin to in - tv cc to enable burst mode operation. connect to ground to enable forced continuous mode of operation. floating this pin will enable pulse-skipping mode. nc (b7-b8, c3-c4): no connection pins. either float these pins or connect them to gnd for thermal purpose. v in (c1, c8, c9, d1, d3-d5, d7-d9 and e8): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. v out (c10-c11, d10-d11, e9-e11, f9-f11, g10-g11): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. sw (c5): switching node of the circuit. this pin is used to check the switching frequency. leave pin floating. a resistor-capacitor snubber can be placed from sw to pgnd to eliminate high frequency switch node ringing. see the applications information section. pgood (c7): output voltage power good indicator. open- drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. v out_lcl (g9): this pin is connected to the top of the internal top feedback resistor for the output. when the remote sense amplifier is used, connect the remote sense amplifier output diffout to v out_lcl to drive the 10k top feedback resistor. when the remote sense amplifier is not used, connect v out_lcl to v out directly. freq (e3): frequency set pin. a 10a current is sourced from this pin. a resistor from this pin to ground sets a voltage, that in turn, programs the operating frequency. alternatively, this pin can be driven with a dc voltage that can set the operating frequency. see the applications in - formation section. the LTM4649 has an internal resistor to program frequency to 450khz. track/ss (e5): output v oltage tracking pin and soft- start inputs. the pin has a 1.2a pull-up current source. a capacitor from this pin to ground will set a soft-start ramp rate. in tracking, the regulator output can be tracked to a different voltage. the different voltage is applied to a voltage divider then the slave outputs track pin. this voltage divider is equal to the slave outputs feedback divider for coincidental tracking. see the applications information section. fb (e7): the negative input of the error amplifier. internally, this pin is connected to v out_lcl with a 10k precision resistor. different output voltages can be programmed with an additional resistor between v fb and ground pins. in polyphase operation, tying the v fb pins together allows for parallel operation. see the applications information section for details. run (f1): run control pin. a voltage above 1.25v will turn on the module. each run pin has a 1a pull-up cur - rent, once the run pin reaches 1.2v an additional 4.5a pull-up current is added to this pin. package row and column labeling may vary among module products. review each package layout carefully. 4649fa LTM4649
8 for more information www.linear.com/LTM4649 p in func t ions clkout (f2): output clock signal for polyphase opera - tion. the phase of clkout is determined by the state of the phmode pin. int v cc (f4): internal 5v ldo for driving the control cir - cuitry and the power mosfet drivers. the 5v ldo has a 100ma current limit. comp (f6): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. tie all comp pins together in parallel operation. diffn (f7): input to the remote sense amplifier. this pin connects to the ground remote sense point. connect to ground when not used. diffp (f8): input to the remote sense amplifier. this pin connects to the output remote sense point. connect to ground when not used. diffout (g8): output of the remote sense amplifier. this pin connects to the v out_lcl pin for remote sense applications. otherwise float when not used. 4649fa LTM4649
9 for more information www.linear.com/LTM4649 b lock diagra m figure 1. simplified LTM4649 block diagram power control 1f v out v in 1m 10k 0.5% freq run v fb gnd comp v out_lcl r2 r1 mode track/ss r fset 115k 6.65k 1% c ss 4649 f01 0.35h m1 v out v out 1.5v 10a v in v in 4.5v to 16v m2 internal comp internal loop filter intv cc 250k diff_out diffp diffn gnd pgood intv cc clkin temp > 1.4v = on < 1.1v = off max = 5v ? ? + + 1f + c in c out + 10k intv cc diff amp 4649fa LTM4649
10 for more information www.linear.com/LTM4649 o pera t ion power module description the LTM4649 is a high performance single output stand - alone nonisolated switching mode dc/dc power supply. it can provide up to 10a output current with few exter - nal input and output capacitors. this module provides precisely regulated output voltage programmable via an external resistor from 0.6vdc to 3.3vdc over a 4.5v to 16v input range. the typical application schematic is shown in figure 17. the LTM4649 has an integrated constant-frequency cur - rent mode regulator, power mosfets, inductor, and other supporting discrete components. the typical switching frequency is 450khz. for switching noise-sensitive ap - plications, it can be externally synchronized from 400khz to 750khz. see the applications information section. with current mode control and internal feedback loop compensation, the LTM4649 module has sufficient stabil - ity margins and good transient per formance with a wide range of output capacitors, especially with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit in an over current condition. an internal over voltage monitor protects the output voltage in the event of an overvoltage >10%. the top mosfet is turned off and the bottom mosfet is turned on until the output is cleared. pulling the run pin below 1.1v forces the regulator into a shutdown state. the track/ss pin is used for program - ming the output voltage ramp and voltage tracking during start-up. see the application information section. the l tm4649 is internally compensated to be stable over all operating conditions. t able 3 provides a guideline for input and output capacitances for several operating con - ditions. the linear technology module power design tool will be provided for transient and stability analysis. the v fb pin is used to program the output voltage with a single external resistor to ground. a remote sense amplifier is provided in the LTM4649 for accurately sensing output voltages 3.3v at the load point. multiphase operation can be easily employed with the synchronization inputs using an external clock source. see application examples. high efficiency at light loads can be accomplished with selectable burst mode operation using the mode pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. a diode connected pnp transistor with base and collector grounded is included in the module as a general purpose single-ended temperature monitor. the temperature monitor is intended to be used as a general temperature monitor, see applications information section the switching node pins are available for functional opera - tion monitoring and a resistor-capacitor snubber circuit can be careful placed on the switching node pin to ground to dampen any high frequency ringing on the transition edges. see the applications information section for details. 4649fa LTM4649
11 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion the typical LTM4649 application circuit is shown in fig - ure?17. external component selection is primarily deter - mined by the maximum load current and output voltage. refer to t able 3 for specific external capacitor requirements for particular applications. v in to v out step-down ratios there are restrictions in the v in to v out step-down ratio that can be achieved for a given input voltage. the v in to v out minimum dropout is a function of load current and at very low input voltage and high duty cycle applications output power may be limited as the internal top power mosfet is not rated for 10a operation at higher ambient temperatures. at very low duty cycles the minimum 110ns on-time must be maintained. see the frequency adjust - ment section and temperature derating curves. output voltage programming the p wm controller has an internal 0.6v 0.5% refer - ence voltage. as shown in the block diagram, a 10k 0.5% internal feedback resistor connects the v out_lcl and v fb pins together. when the remote sense amplifier is used, then diffout is connected to the v out_lcl pin. if the remote sense amplifier is not used, then v out_lcl connects to v out . the output voltage will default to 0.6v with no feedback resistor. adding a resistor r fb from v fb to ground programs the output voltage: v out = 0.6v ? 10k + r fb r fb table 1. v fb resistor table vs various output voltages v out (v) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 r fb (k) open 15 10 6.65 4.99 3.09 2.21 for parallel operation of n LTM4649, the following equa - tion can be used to solve for r fb : r fb = 10k n v out 0.6 ? 1 in parallel operation the v fb pins have an i fb current of 20na maximum each channel. to reduce output voltage error due to this current, an additional v out_lcl pin can be tied to v out , and an additional r fb resistor can be used to lower the total thevenin equivalent resistance seen by this current. input capacitors the LTM4649 module should be connected to a low ac impedance dc source. additional input capacitors are needed for the rms input ripple current rating. the i cin(rms) equation which follows can be used to calculate the input capacitor requirement. typically 22f x7r ceramics are a good choice with rms ripple current ratings of ~2a each. a 47f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty cycle can be estimated as: d = v out v in without considering the inductor ripple current, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1 ? d ( ) in the previous equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher-rat - ed electrolytic aluminum capacitor or a polymer capacitor. output capacitors the l tm4649 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require - ments. c out can be a low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitors. the typical output capacitance range is from 200f to 470f. additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is 4649fa LTM4649
12 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion required. table 3 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 3 matrix, and the linear technology module power design tool will be provided for stability analysis. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. the linear technology module power design tool can calculate the output ripple reduction as the number of implemented phases increases by n times. burst mode operation the LTM4649 is capable of burst mode operation in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. to enable burst mode operation, simply tie the mode pin to intv cc . during burst mode operation, the peak current of the inductor is set to approximately 30% of the maxi - mum peak current value in normal operation even though the voltage at the comp pin indicates a lower value. the voltage at the comp pin drops when the inductor s aver - age current is greater than the load requirement. as the comp voltage drops below 0.5v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfet s. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. the load current is now being supplied from the output capacitors. when the output voltage drops, causing comp to rise, the internal sleep line goes low, and the LTM4649 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation in applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. pulse-skipping operation allows the LTM4649 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. floating the mode pin enables pulse-skipping operation. with pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping opera - tion cycles. this mode has lower ripple than burst mode operation and maintains a higher frequency operation than burst mode operation. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency , and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode pin to ground. in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4649s output voltage is in regulation. frequency selection the LTM4649 device is internally programmed to 450khz switching frequency to improve power conversion effi - ciency. it is recommended for all of the application of low v in or low v out . for the application with high v in (v in > = 12v) and high v out (v out > = 1.8v), a higher 750khz frequency is recommended to limit inductor ripple cur - rent by simply tie freq to intv cc . table 3 listed different frequency and freq pin recommendations for different v in , v out conditions. if desired, a resistor can be connected from the freq pin to intv cc to adjust the freq pin dc voltage to increase the switching frequency between default 450khz and maximum 750khz by. figure 2 shows a graph of frequency setting verses freq pin dc voltage. figure 18 shows an example of frequency programmed to 650khz. please be aware freq pin has an accurate 10a current sourced from this pin when calculate the resistor value. 4649fa LTM4649
13 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion pll and frequency synchronization the LTM4649 device operates over a range of frequen - cies to improve power conversion efficiency. the nominal switching frequency is 450khz. it can also be synchronized from 400khz to 750khz with an input clock that has a high level above 2v and a low level below 0.8v at the clkin pin. once the LTM4649 is synchronizing to an external clock frequency, it will always be running in forced continuous operation. the 400khz low end operation frequency limit is put in place to limit inductor ripple current. multiphase operation for outputs that demand more than 10a of load current, multiple LTM4649 devices can be paralleled to provide more output current and reduced input and output voltage ripple. the clkout signal together with clkin pin can be used to cascade additional power stages to achieve the multi - phase power supply solution. tying the phmode pin to int v cc , gnd, or (floating) generates a phase difference (between clkin and clkout) of 180, 120, or 90 respectively as shown in table 2. a total of 4 phases can be cascaded to run simultaneously with respect to each other by programming the phmode pin of each LTM4649 channel to different levels. figure 3 shows a 3-phase de - sign and 4-phase design example for clock phasing with the phasmd table. table 2. phasemd and clkout signal relationship phasemd gnd float intv cc clkout 120 90 180 the LTM4649 device is an inherently current mode con - trolled device, so parallel modules will have good current sharing. this will balance the thermals in the design. t ie the comp , v fb , track/ss and run pins of each LTM4649 together to share the current evenly. figures 19 and 20 show a schematic of the parallel design. a multiphase power supply could significantly reduce the amount of ripple current in both the input and output capacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used. 4649 f03 4-phase design 3-phase design 90 degree 90 degree 90 degree 0 phase float float float float clkin v out phasmd clkout 90 phase clkin v out phasmd clkout 180 phase clkin v out phasmd clkout 270 phase clkin v out phasmd clkout 120 degree 120 degree 0 phase gnd gnd gnd clkin v out phasmd clkout 120 phase clkin v out phasmd clkout 240 phase clkin v out phasmd clkout figure 3. examples of 3-phase, 4-phase operation with phasmd table freq pin voltage (v) 0 frequency (khz) 900 800 600 400 100 200 700 500 300 0 2 4649 f02 2.5 1 1.5 0.5 figure 2. operating frequency vs freq pin voltage 4649fa LTM4649
14 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases (see figure 4). minimum on-t ime minimum on-time t on is the smallest time duration that the LTM4649 is capable of turning on the top mosfet. it is determined by internal timing delays, and the gate charge required turning on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: v out v in ? freq > t on(min) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple and current will increase. the minimum on-time can be increased by lowering the switching fre - quency. a good rule of thumb is to use an 110ns on-time. soft-start the track/ss pin of the master can be controlled by a capacitor placed on the master regulator track/ss pin to ground. a 1.2a current source will charge the track/ ss pin up to the reference voltage and then proceed up to intv cc . after the 0.6v ramp, the track/ss pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. the track/ss pins are pulled low when the run pin is below 1.2v. the total soft-start time can be calculated as: t ss = c ss 1.2a ? ? ? ? ? ? ? 0.6 duty factor (v o /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4649 f04 rms input ripple current dc load current 1-phase 2-phase 3-phase 4-phase 6-phase figure 4. input rms current ratios to dc load current as a function of duty cycle 4649fa LTM4649
15 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion regardless of the mode selected by the mode pin, the regulator channels will always start in pulse-skipping mode up to track/ss = 0.5v. between track/ss = 0.5v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once track/ss > 0.54v. in order to track with another channel once in steady state operation, the LTM4649 is forced into continuous mode operation as soon as v fb is below 0.54v regardless of the setting on the mode pin. output voltage tracking output voltage tracking can be programmed externally using the track/ss pins. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider to implement coincident tracking. the LTM4649 uses an accurate 10k 0.5% resistor internally for the top feedback resistor for each channel. figure 6 shows an example of coincident tracking. equations: v slave = 1 + 10k r ta ? ? ? ? ? ? ? v track v track is the track ramp applied to the slaves track pin. v track has a control range of 0v to 0.6v, or the internal reference voltage. when the masters output is divided down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. voltage tracking is disabled when v track is more than 0.6v. rta in figure 5 will be equal to the r fb for coincident tracking. figure 6 shows the coincident tracking waveforms. ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the masters comp track/ss run freq mode pgood v out v out_lcl diffout diffp diffn v fb LTM4649 v in r2 10k r fb1 6.65k c10 22f 16v c7 22f 16v c ss soft-start capacitor v out2 1.5v 10a c11 100f 6.3v 2 intv cc v in gnd comp track/ss run freq mode pgood v out v out_lcl diffout diffp diffn v fb LTM4649 v in r1 10k r fb 10k c2 22f 16v c3 22f 16v c6 100f 6.3v 2 v out1 1.2v 10a intv cc 4649 f05 gnd r tb 10k r ta 10k master ramp or output v in figure 5. dual outputs (1.5v and 1.2v) with tracking 4649fa LTM4649
16 for more information www.linear.com/LTM4649 output voltage (v) time master output slave output 4649 f06 figure 6. output coincident tracking waveform a pplica t ions i n f or m a t ion track/ss pin. as mentioned above, the track/ss pin has a control range from 0v to 0.6v. the masters track/ ss pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: mr sr ? 10k = r tb where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal the 10k. r ta is derived from equation: r ta = 0.6v v fb 10k + v fb r fb ? v track r tb where v fb is the feedback voltage reference of the regula - tor, and v track is 0.6v. since r tb is equal to the 10k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r ta is equal to r fb with v fb = v track . therefore r tb = 10k, and r ta = 10k in figure 5. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. each of the track/ss pins will have the 1.3a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track/ss pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 10k is used then a 1.0k can be used to reduce the track/ss pin offset to a negligible value. power good the pgood pins are open-drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 7.5% window around the regulation point. a resistor can be pulled up to a particular supply voltage no greater than 6v maximum for monitoring. stability compensation the module has already been internally compensated for all output voltages. table 3 is provided for most ap - plication requirements. the linear technology module power design tool will be provided for other control loop optimization. run enable the run pin has an enable threshold of 1.35v maximum, typically 1.22v with 80mv of hysteresis. it controls the turn-on of the module. the run pin can be pulled up to v in for 5v operation, or a 5v zener diode can be placed on the pin and a 10k to 100k resistor can be placed up to higher than 5v input for enabling the module. the run pin can also be used for output voltage sequencing. in parallel operation the run pins can be tied together and controlled from a single control. see the typical applica - tion circuits in figures 19 and 20. the run pin can also be left floating. the run pin has a 1a pull-up current sour ce that increases to 4.5a during ramp-up. differential remote sense amplifier an accurate differential remote sense amplifier is provided in the LTM4649 to sense low output voltages accurately at the remote load points. this is especially true for high current loads. it is very important that the diffp and diffn are connected properly at the output, and diffout is connected to v out_lcl . review the parallel schematics in figures 19 and 20. 4649fa LTM4649
17 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion sw pins the sw pin is generally for testing purposes by monitor - ing the pin. the sw pin can also be used to dampen out switch node ringing caused by lc parasitic in the switched current path. usually a series r-c combination is used called a snubber cir cuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor . if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre - quency can be measured for its value. the impedance z can be calculated: z l = 2 ? f ? l where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z c = 1 2 ? f ? c these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount the power loss. temperature monitoring measuring the absolute temperature of a diode is pos - sible due to the relationship between current, voltage and temperature described by the classic diode equation: i d = i s ? e v d ? v t ? ? ? ? ? ? or v d = ? v t ? ln i d i s where i d is the diode current, v d is the diode voltage, is the ideality factor (typically close to 1.0) and i s (satura- tion current) is a process dependent parameter. v t can be broken out to: v t = k ? t q where t is the diode junction temperature in kelvin, q is the electron charge and k is boltzmanns constant. v t is approximately 26mv at room temperature (298k) and scales linearly with kelvin temperature. it is this linear temperature relationship that makes diodes suitable temperature sensors. the i s term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, and by definition must always be less than i d . combining all of the constants into one term: k d = ? k q where k d = 8.62 ?5 , and knowing ln(i d /i s ) is always posi - tive because i d is always greater than i s , leaves us with the equation that: v d = t(kelvin) ? k d ? ln i d i s where v d appears to increase with temperature. it is com - mon knowledge that a silicon diode biased with a current sour ce has an approximately C2mv /c temperature rela - tionship (figure 7), which is at odds with the equation. in fact, the i s term increases with temperature, reducing the ln(i d /i s ) absolute value yielding an approximately C2mv/c composite diode voltage slope. an external diode connected pnp transistor can be pulled up to v in with a resistor to set the current to 100a for using this diode connected transistor as a general tem - perature monitor by monitoring the diode voltage drop with temperature. see figure 21 for an example. 4649fa LTM4649
18 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param - eters defined by jesd51-9 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per formed on a module package mounted to a hardware test boardalso defined by jesd51-9 (test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients in found in jesd51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulators thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are in-and-of themselves not relevant to providing guidance of thermal per formance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to ones application usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section typically gives four thermal coefficients explicitly defined in jesd 51-12; these coef - ficients are quoted or paraphrased below: 1. ja : the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom : the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 3. jctop : the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb : the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a por - tion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. 4649 f07 temperature (c) ?173 ?73 27 127 diode voltage (v) 0.4 0.6 0.8 1.0 ?v d i d = 100a figure 7. diode voltage v d vs temperature t(c) for different bias currents 4649fa LTM4649
19 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion a graphical representation of the aforementioned ther - mal resistances is given in figure 8; blue resistances are contained within the module regulator , whereas green resistances are external to the module regulator . as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclu - sively through the top or exclusively through bottom of the moduleas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within a sip (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicitybut also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the module and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined jedec environment consistent with jsed51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the module with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory test have been performed and correlated to the module model, then the jb and ba are summed together to correlate quite well with the module model with no figure 8. graphical representation of jesd51-12 thermal coefficients 4649 f08 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance 4649fa LTM4649
20 for more information www.linear.com/LTM4649 figure 9. 5v in , 3.3v out and 1.5v out power loss figure 10. 12v in , 3.3v out and 1.5v out power loss a pplica t ions i n f or m a t ion figure 11. no heat sink with 5v in to 1.5v out figure 12. no heat sink with 12v in to 1.5v out figure 13. no heat sink with 5v in to 3.3v out figure 14. no heat sink with 12v in to 3.3v out airflow or heat sinking in a properly define chamber. this jb + ba value is shown in the pin configuration sec - tion and should accurately equal the ja value because approximately 100% of power loss flows from the junc - tion through the board into ambient with no airflow or top mounted heat sink. the 5v in and 12v in power loss curves in figures 9 and?10 can be used in coordination with the load current derating curves in figures 11 to 14 for calculating an approximate ja thermal resistance for the LTM4649 with various heat sinking and airflow conditions. the power loss curves are taken at room temperature, and are increased with a multiplicative factor according to the ambient temperature. this approximate factor is: 1.4 for 120c. the derating cur ves are plotted with the output current starting at 10a and the ambient temperature at 40c. the output voltages are 1.5v and 3.3v. these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal mod - eling analysis. the junction temperatures are monitored load current (a) 0 0 power loss (w) 0.5 1.0 1.5 2.0 2.5 3.0 2 4 6 8 4649 f09 10 v out = 3.3v v out = 1.5v load current (a) 0 0 power loss (w) 0.5 1.0 1.5 2.0 2.5 3.0 2 4 6 8 4649 f10 10 v out = 3.3v v out = 1.5v ambient temperature (c) 0 0 load current (a) 2 4 6 8 12 20 40 60 80 4649 f11 100 120 10 400lfm 200lfm 0lfm ambient temperature (c) 0 0 load current (a) 2 4 6 8 12 20 40 60 80 4649 f12 100 120 10 400lfm 200lfm 0lfm ambient temperature (c) 0 0 load current (a) 2 4 6 8 12 20 40 60 80 4649 f13 100 120 10 400lfm 200lfm 0lfm ambient temperature (c) 0 0 load current (a) 2 4 6 8 12 20 40 60 80 4649 f14 100 120 10 400lfm 200lfm 0lfm 4649fa LTM4649
21 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example in figure?12 the load current is derated to ~8a at ~90c with no air or heat sink and the power loss for the 12v to 1.5v at 8a output is about 2.24w. the 2.24w loss is calculated with the 1.6w room temperature loss from the 12v to 1.5v power loss curve at 8a, and the 1.40 multiplying factor at 120c junction. if the 90c ambient temperature is subtracted from the 120c junction temperature, then the difference of 30c divided by 2.24w equals a 13c/w ja thermal resistance. table 4 specifies a 14c/w value which is very close. table?4 and table 5 provide equivalent thermal resistances for 1.5v and 3.3v outputs with and without airflow. the derived thermal resistances in tables?4 and 5 for the various con - ditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the ef - ficiency curves in the typical performance characteristics section and adjusted with the above ambient temperature multiplicative factors. the printed cir cuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm. safety considerations the LTM4649 module does not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. figure 15. thermal image 12v to 1.5v at 10a (no heat sink, no air flow. at room temperature ambient) 48.1c 48.8c 4649 f15 4649fa LTM4649
22 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion figure 16. recommended pcb layout v out gnd c out c in v in 4649 f16 gnd layout checklist/example the high integration of LTM4649 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout con - siderations are still necessary. ? use large pcb copper areas for high current path, including v in , gnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , gnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on the pads, unless they are capped. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. figure 16 gives a good example of the recommended layout. 4649fa LTM4649
23 for more information www.linear.com/LTM4649 a pplica t ions i n f or m a t ion table 3. output voltage response vs component matrix (refer to figure 18) 0a to 5a load step typical measured values c in (bulk)* vendors part number c in (ceramic) vendors part number c out (ceramic) vendors part number 150f, 16v sanyo oscon 25hvh150mt 22f, 16v murata grm32er71c226ke18l 100f, 6.3v murata grm32er60j107me20l 220f, 4v murata grm31cr60g227m v out v in c in (bulk)* c in (ceramic) c out (ceramic) c ff load step v droop v p-p recovery time load step speed r fb sw freq freq pin 1v 5v, 12v 120f* 22f 2 100f 3 none 75% to 100% 45mv 90mv 40s 1a/s 15k 450khz float 1.2v 5v, 12v 120f* 22f 2 100f 3 none 75% to 100% 50mv 100mv 50s 1a/s 10k 450khz float 1.5v 5v, 12v 120f* 22f 2 100f 3 none 75% to 100% 57mv 114mv 60s 1a/s 6.65k 450khz float 2.5v 5v 120f* 22f 2 100f 3 none 75% to 100% 75mv 150mv 70s 1a/s 3.16k 450khz float 2.5v 12v 120f* 22f 2 100f 3 none 75% to 100% 75mv 150mv 70s 1a/s 3.16k 750khz intv cc 3.3v 5v 120f* 22f 2 100f 3 none 75% to 100% 95mv 190mv 70s 1a/s 2.21k 450khz float 3.3v 12v 120f* 22f 2 100f 3 none 75% to 100% 95mv 190mv 70s 1a/s 2.21k 750khz intv cc 1v 5v, 12v 120f* 22f 2 220f 2 none 50% to 100% 70mv 140mv 30s 1a/s 15k 450khz float 1.2v 5v, 12v 120f* 22f 2 220f 2 none 50% to 100% 75mv 150mv 40s 1a/s 10k 450khz float 1.5v 5v, 12v 120f* 22f 2 220f 2 none 50% to 100% 90mv 180mv 40s 1a/s 6.65k 450khz float 2.5v 5v 120f* 22f 2 220f 2 none 50% to 100% 135mv 270mv 50s 1a/s 3.16k 450khz float 2.5v 12v 120f* 22f 2 220f 2 none 50% to 100% 135mv 270mv 50s 1a/s 3.16k 750khz intv cc 3.3v 5v 120f* 22f 2 220f 2 none 50% to 100% 175mv 350mv 60s 1a/s 2.21k 450khz float 3.3v 12v 120f* 22f 2 220f 2 none 50% to 100% 175mv 350mv 60s 1a/s 2.21k 750khz intv cc *bulk capacitor is optional if v in has very low input impedance. table 4. 1.5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 11, 12 5, 12 figure 9 0 none 14 figures 11, 12 5, 12 figure 9 200 none 12 figures 11, 12 5, 12 figure 9 400 none 10 table 5. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 13, 14 5, 12 figure 10 0 none 14 figures 13, 14 5, 12 figure 10 200 none 12 figures 13, 14 5, 12 figure 10 400 none 10 4649fa LTM4649
24 for more information www.linear.com/LTM4649 typical a pplica t ions figure 17. 4.5v to 16v in , 1.5v at 10a design figure 18. 4.5v to 16v v in , 3.3v out at 8a design with increased 650khz frequency v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd c1 0.1f c out1 100f 6.3v r fb 6.65k 4649 f17 c out2 100f 6.3v c in 22f 16v v in 4.5v to 16v v out 1.5v 10a clkout v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq 1m LTM4649 gnd c1 0.1f 100f 6.3v 2 r fb 2.21k 4649 f18 c in 22f 16v c in 22f 16v v in 4.5v to 16v v out 3.3v 8a clkout 4649fa LTM4649
25 for more information www.linear.com/LTM4649 typical a pplica t ions figure 19. three LTM4649 in parallel, 1.5v at 30a design v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd c1 0.1f c out1 100f 6.3v r fb 6.65k c out2 100f 6.3v c in1 22f 16v v in 4.5v to 16v run v out 1.5v 30a clkout v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood LTM4649 gnd c out3 100f 6.3v c out5 100f 6.3v pgood 4649 f19 c out4 100f 6.3v c in2 22f 16v clkout v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood LTM4649 gnd c out6 100f 6.3v c in3 22f 16v clkout clkin freq clkin freq 4649fa LTM4649
26 for more information www.linear.com/LTM4649 typical a pplica t ions figure 20. quad outputs 4-phase LTM4649 regulator with tracking function figure 21. single LTM4649 10a design with temperature monitoring v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd c1 0.1f c out1 100f 6.3v r1 2.21k c out2 100f 6.3v c in1 22f 16v v in 4.5v to 16v v out1 3.3v 8a clkout v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq v out1 v out1 v out1 LTM4649 gnd c out3 100f 6.3v r2 3.09k c out4 100f 6.3v c in2 22f 16v r3 10k r4 3.09k v out2 2.5v 10a clkout v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd c out7 100f 6.3v r2 6.65k 4649 f20 c out8 100f 6.3v c in4 22f 16v r9 10k r10 6.65k v out4 1.5v 10a clkout v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin LTM4649 gnd c out5 100f 6.3v r5 4.99k c out6 100f 6.3v c in3 22f 16v r6 10k r7 4.87k v out3 1.8v 10a clkout freq v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd c1 0.1f c out1 100f 6.3v r fb 6.65k r7 4649 f21 c out2 100f 6.3v c in 22f 16v 0.1f v in 4.5v to 16v v out 1.5v 10a clkout a/d uc v in v in 100a r7 = 4649fa LTM4649
27 for more information www.linear.com/LTM4649 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes 1 2 3 4 5 6 7 8 9 10 11 pin 1 bga package 68-lead (15.00mm 9.00mm 4.92mm) (reference ltc dwg# 05-08-1892 rev a) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition can be 96.5% sn/3.0% ag/0.5% cu or sn pb eutectic 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (68 places) detail b substrate a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.72 0.50 4.22 0.60 0.60 0.27 3.95 nom 4.92 0.60 4.32 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.32 4.00 max 5.12 0.70 4.42 0.90 0.66 0.37 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 68 a2 d e e b f g suggested pcb layout top view 0.000 3.810 5.080 3.810 6.350 5.080 6.350 2.540 1.270 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 // bbb z z h2 h1 0.630 0.025 ? 68x bga 68 1212 rev a tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module g f e d c b a 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes 4649fa LTM4649
28 for more information www.linear.com/LTM4649 p ackage descrip t ion p ackage pho t o LTM4649 bga pinout pin id function pin id function pin id function pin id function pin id function pin id function pin id function a1 gnd b1 gnd c1 v in d1 v in e1 gnd f1 run g1 gnd a2 gnd b2 C c2 C d2 C e2 C f2 clckout g2 gnd a3 gnd b3 clkin c3 nc d3 v in e3 freq f3 gnd g3 gnd a4 gnd b4 phmode c4 nc d4 v in e4 C f4 intvcc g4 gnd a5 gnd b5 mode c5 sw d5 v in e5 track/ss f5 gnd g5 gnd a6 temp b6 C c6 C d6 C e6 C f6 comp g6 gnd a7 gnd b7 nc c7 pgood d7 v in e7 fb f7 diffn g7 gnd a8 gnd b8 nc c8 v in d8 v in e8 v in f8 diffp g8 diffout a9 gnd b9 gnd c9 v in d9 v in e9 v out f9 v out g9 v out_lcl a10 gnd b10 gnd c10 v out d10 v out e10 v out f10 v out g10 v out a11 gnd b11 gnd c11 v out d11 v out e11 v out f11 v out g11 v out package row and column labeling may vary among module products. review each package layout carefully. 4649fa LTM4649
29 for more information www.linear.com/LTM4649 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 2/14 added snpb (lead) bga package figures 9 and 10 changed y-axis to power loss (w) 1, 2 20 4649fa LTM4649
30 for more information www.linear.com/LTM4649 ? linear technology corporation 2013 lt 0214 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTM4649 r ela t e d p ar t s typical a pplica t ion figure 22. dual output 1.2v, 1.8v 2-phase LTM4649 regulator with tracking v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd c out2 100f 6.3v c out1 100f 6.3v r1 10k r2 10k r3 10k c in1 22f 16v v in 4.5v to 16v master slope intv cc intv cc v out 1.2v 10a clkout clock v in intv cc sw run mode phmode track/ss temp v out v out_lcl diffout diffp diffn v fb comp pgood clkin freq LTM4649 gnd c out4 100f 6.3v c out3 100f 6.3v r4 4.99k c in2 22f 16v v out 1.8v 10a clkout 4649 f22 part number description comments ltm4627 20v, 15a step-down module regulator 4.5v v in 20v, 0.6v v out 5v, pll input, remote sense amplifier, v out tracking, 15mm 15mm 4.3mm lga and 15mm 15mm 4.9mm bga ltm4620a dual 16v, 13a or single 26a step-down module regulator 4.5v v in 16v, 0.6v v out 5.3v, pll input, remote sense amplifier, v out tracking, 15mm 15mm 4.41mm lga ltm4613 36v in , 8a en55022 class b certified dc/dc step-down module regulator 5v v in 36v, 3.3v v out 15v, pll input, v out tracking and margining, 15mm 15mm 4.32mm lga ltm8045 inverting or sepic module dc/dc converter with up to 700ma output current 2.8v v in 18v, 2.5v v out 15v, synchronizable, 6.25mm 11.25mm 4.92mm bga l tm8061 32v , 2a step-down module battery charger with programmable input current limit cc-cv charging single and dual cell li-ion or li-poly batteries, 4.95v v in 32v, c/10 or adjustable timer charge termination, 9mm 15mm 4.32mm lga l tm8048 1.5w , 725vdc galvanically isolated module converter with ldo post regulator 3.1v v in 32v, 2.5v v out 12v, 1mv pp output ripple, internal isolated transformer, 9mm 11.25mm 4.92mm bga ltc2974 quad digital power supply manager with eeprom i 2 c/pmbus interface, configuration eeprom, fault logging, per channel voltage, current and temperature measurements design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. 4649fa LTM4649

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